PCIe

PCI Express (Peripheral Component Interconnect Express), commonly abbreviated as PCIe, is a high-speed serial expansion bus standard that replaced the older PCI, PCI-X, and AGP bus standards. Unlike its parallel predecessors, PCIe uses a point-to-point topology in which each device has a dedicated connection to the root complex, eliminating the bus contention and arbitration overhead that limited parallel bus scalability. Each PCIe connection consists of one or more lanes, each lane being a full-duplex differential pair carrying 1 bit per direction per clock cycle.

The architectural significance of PCIe extends far beyond its role as a peripheral interconnect. PCIe is the physical layer upon which modern Unified Memory architectures are built. NVIDIA's NVLink, Intel's CXL, and AMD's Infinity Fabric all leverage PCIe's electrical and protocol specifications to implement cache-coherent memory sharing between processors and accelerators. The CXL protocol, in particular, runs directly over PCIe 5.0 and 6.0 physical layers, using the same lanes and connectors to transport memory semantics rather than traditional I/O transactions. This convergence — using the same physical infrastructure for both I/O and memory coherence — is one of the most consequential architectural shifts in computing since the transition from multi-drop buses to switched fabrics.

PCIe's evolution reflects the broader systems trend toward serialization and packetization. Where parallel buses widened to increase bandwidth (32-bit PCI, 64-bit PCI-X), PCIe increases bandwidth by adding lanes and raising the signaling rate. PCIe 6.0 achieves 64 GT/s per lane using PAM4 signaling, doubling the bandwidth of PCIe 5.0 without requiring additional pins. This lane-scaling model is more power-efficient and physically tractable than widening, but it imposes new constraints on trace length, signal integrity, and thermal management. The connector itself has become a systems problem.

PCIe is often treated as a boring infrastructure detail — the plumbing of the computer that engineers must tolerate but need not understand. This is a profound misreading. PCIe is the substrate of modern systems integration. The decision to build CXL on top of PCIe rather than invent a new physical layer was not an engineering shortcut; it was a declaration that the future of computing belongs to systems that can repurpose existing infrastructure for new semantic purposes. The PCIe lane is not just a wire; it is an abstraction boundary that the entire industry has agreed to respect. And in a field as fragmented as computer architecture, shared abstractions are more valuable than optimal ones.