GAAFET

A GAAFET (gate-all-around field-effect transistor) is the next evolutionary step beyond the FinFET in the scaling of CMOS logic. Where a FinFET wraps the gate electrode around three sides of a raised silicon fin, a GAAFET wraps the gate entirely around the channel — forming a nanosheet, nanowire, or nanoribbon that is enclosed by the gate electrode on all sides. This complete electrostatic enclosure provides superior control over the channel, suppressing leakage currents more effectively than FinFETs and enabling further scaling to gate lengths below 3 nanometers.

The GAAFET architecture was pioneered by researchers at IBM, CEA-Leti, and IMEC, with Samsung announcing the first commercial GAAFET process (branded 'Multi-Bridge-Channel FET' or MBCFET) for its 3nm node in 2022. TSMC and Intel are expected to introduce GAAFET architectures at their 2nm nodes. The transition from FinFET to GAAFET is driven by the same scaling imperative: as gate lengths shrink, short-channel effects become more severe, and the gate must exert greater control over the channel to maintain the sharp on-off transitions that make digital logic possible.

The manufacturing of GAAFETs is more complex than FinFETs. The channel material must be formed into suspended nanosheets or nanowires, which requires precise etching and release processes. The gate dielectric must wrap uniformly around the channel without thinning at the corners, which would create localized breakdown. The variability between nanosheets introduces new sources of process variation that must be managed through design-technology co-optimization (DTCO). These challenges are not insurmountable, but they require advances in fabrication equipment, materials, and design methodologies that extend the CMOS ecosystem rather than replacing it.

From a systems perspective, the GAAFET represents the third dimension of the transistor scaling story. Planar transistors were two-dimensional: a gate on top of a channel. FinFETs added height. GAAFETs add enclosure. Each dimension added has extended the scaling trajectory by improving the gate's control over the channel without requiring fundamentally new materials or physics. The question is whether GAAFETs will provide enough scaling headroom to reach the 1nm node and beyond, or whether they will be the last geometric refinement before the industry must transition to new materials or new paradigms entirely.

The GAAFET is the final geometric maneuver of the CMOS era. When the gate has wrapped around the channel on all sides, there are no more directions to expand. What remains is the atom — and after that, the electron.