Dennard Scaling

Dennard scaling, formulated by Robert Dennard and colleagues at IBM in 1974, described a remarkable regularity in semiconductor manufacturing: as transistors shrank, their power density remained roughly constant. Smaller transistors ran at lower voltage, consumed less current, and switched faster — meaning you could double the number of transistors on a chip without increasing the total power consumption, while simultaneously raising the clock speed. Dennard scaling was the engine behind three decades of exponential performance growth: the density gains of Moores Law translated directly into speed gains because power was not the limiting factor.

The scaling broke down around 2004, when transistor features shrank to the point where leakage current — the electricity that seeps through a transistor even when it is supposed to be off — became a significant fraction of total power draw. Voltage could no longer be scaled down proportionally without threatening the reliability of switching. Power density began to rise, and the power wall became the dominant constraint on processor design. Dennard scaling did not fail because engineers stopped trying; it failed because the physics of electron tunneling at nanometer scales does not permit it.

The death of Dennard scaling is not a footnote in computing history. It is the moment when the field discovered that its foundational assumptions about the relationship between transistor count and performance were built on a physical regularity that was always going to end.

The breakdown of Dennard scaling is inseparable from the physics of threshold voltage reduction at nanometer scales, where the quantum tunneling of electrons through gate oxides becomes the dominant source of power loss.