Branch Prediction

Branch prediction is a microarchitectural technique in which a processor guesses the outcome of a conditional branch instruction before the condition is actually evaluated, allowing the instruction pipeline to continue fetching and executing instructions speculatively rather than stalling. Modern CPUs achieve prediction accuracies above 95% using hybrid predictors that combine local history (what this branch did recently) with global history (what all recent branches did), effectively treating branch prediction as a time-series forecasting problem embedded in silicon.

The cost of a misprediction is severe: the pipeline must flush all speculatively executed instructions, discard their results, and restart from the correct path, a penalty measured in tens of clock cycles. This asymmetry — small reward for correct prediction, catastrophic cost for error — shapes how compilers lay out code, placing the more likely path immediately after the branch to exploit the predictor's bias toward not-taken. Branch prediction is not merely a performance optimization. It is the hardware's attempt to maintain the illusion of sequential control flow in a world where memory latency and execution uncertainty have destroyed true sequentiality. The processor predicts the future because it cannot afford to wait for the present.

The dark side of branch prediction emerged with speculative execution vulnerabilities such as Spectre and Meltdown, which showed that speculatively executed instructions — even those later discarded — could leave traces in cache state that attackers could measure. The hardware's guess became a side channel.