Heterogeneous Computing
Heterogeneous computing is the use of multiple types of processors — CPUs, GPUs, AI accelerators, and specialized co-processors — within a single computational system. Unlike homogeneous multiprocessing, which replicates identical cores, heterogeneous computing combines fundamentally different execution models, each optimized for a different class of workload. The challenge is not merely hardware integration but programming model integration: how to express a single computation that transparently spans processors with different instruction set architectures, memory models, and synchronization primitives.
The rise of heterogeneous computing is not a design choice made in a vacuum. It is the architectural response to the end of Dennard scaling, the arrival of the power wall, and the proliferation of dark silicon. When every transistor cannot be powered simultaneously, the question becomes not "how many cores can we fit?" but "which cores should we power, and for what workload?" Homogeneous multicore — packing identical cores — assumes every workload benefits from the same kind of execution. This assumption failed. A neural network inference task needs matrix multiplication at scale; a web server needs fast context switching and low latency; a real-time control system needs deterministic timing. No single core design serves all three well.
The Architectural Spectrum
Modern heterogeneous systems span a spectrum from tightly coupled to loosely coupled integration:
- Integrated CPU-GPU systems (AMD APU, Apple Silicon) place CPU and GPU cores on the same die, sharing memory through a unified memory architecture. The tight coupling minimizes data movement but complicates cache coherence and introduces contention.
- Discrete accelerator attachment (NVIDIA DGX, Google TPU pods) connects specialized accelerators via PCIe or NVLink. The loose coupling preserves flexibility but creates a memory bottleneck: data must be explicitly moved between host and device memory, and the programmer (or runtime) must manage the choreography.
- Chiplets and domain-specific architectures (AMD EPYC, Intel Ponte Vecchio) decompose a processor into specialized tiles — compute tiles, I/O tiles, memory tiles — each optimized for its function. The chiplet approach is heterogeneous computing at the sub-die level, where the "processors" are not full CPUs but specialized functional blocks.
- Neuromorphic and analog computing (Intel Loihi, IBM TrueNorth) represents the far end of the spectrum: processors that do not execute conventional instruction streams at all but implement spiking neural networks or analog matrix operations. These devices are not accelerators in the conventional sense; they are alternative computational substrates.
The Programming Model Crisis
Hardware heterogeneity is useless without software that can exploit it. The central challenge of heterogeneous computing is the programming model crisis: how to write a single program that runs efficiently across processors with different ISAs, memory models, and performance characteristics.
Early approaches (CUDA, OpenCL) required the programmer to explicitly partition work between host and device, manage memory transfers, and handle synchronization. This is effective for expert programmers working on stable algorithms but fails for general-purpose software where the optimal partition depends on input data and runtime conditions.
More recent approaches (SYCL, oneAPI, Apache TVM) aim for "single-source" programming: the programmer writes code in a unified language, and the compiler/runtime system partitions it across available devices. The promise is portability with performance; the reality is that automatic partitioning is still inferior to hand-tuned code for most workloads. The compiler cannot know what the programmer knows about data locality, access patterns, and algorithmic structure.
The deepest problem is that the performance model of heterogeneous systems is not compositional. On a homogeneous multicore, you can estimate the speedup of adding more cores by applying Amdahl's law. On a heterogeneous system, the speedup of adding a GPU depends on what fraction of the workload is GPU-friendly, what the data transfer costs are, how the CPU and GPU contend for shared memory, and whether the GPU's execution model (SIMD, SIMT, systolic array) matches the algorithm's parallelism structure. There is no simple formula.
The Memory Problem
Heterogeneous computing intensifies the memory wall problem. When multiple processors with different memory access patterns share a memory hierarchy, the cache coherence protocols designed for homogeneous systems break down. A GPU's memory access pattern (coalesced, streaming, predictable) is the opposite of a CPU's (scattered, latency-sensitive, unpredictable). Unified memory architectures try to bridge this gap but introduce complexity: when the GPU writes to a cache line that the CPU has cached, the coherence protocol must invalidate the CPU's copy. The overhead of maintaining coherence across heterogeneous devices can consume the performance gains of heterogeneity itself.
This has led to a divergence in memory architecture. Some systems (Apple Silicon, NVIDIA Grace) pursue deep hardware integration: unified memory with hardware-managed coherence. Others (discrete GPU systems) abandon coherence across the host-device boundary and rely on explicit synchronization. The choice is not merely technical; it is a bet about what kind of software will dominate. Deep integration favors workloads where data flows continuously between CPU and GPU. Explicit synchronization favors workloads where CPU and GPU operate on distinct phases with clear handoff points.
Heterogeneous Computing and the Limits of Silicon
Heterogeneous computing is sometimes presented as a temporary workaround — a stopgap until a new technology (optical computing, quantum computing, neuromorphic chips) makes the power wall irrelevant. This framing is wrong. Heterogeneous computing is not a workaround; it is the mature form of computation in a world where the substrate is physically constrained and workloads are intrinsically diverse.
Even if a new substrate eliminated the power wall, workloads would still be diverse. A quantum computer is spectacularly efficient for certain problems and spectacularly useless for others. A neuromorphic chip excels at pattern recognition and fails at symbolic reasoning. The future of computation is not a single dominant technology but a federation of specialized technologies, integrated by software that understands their relative strengths.
The bet that homogeneous computing made — that one architecture could serve all workloads — was always contingent on the economics of transistor scaling. When transistors were cheap and power was free, replicating the same core was the optimal strategy. When power became the binding constraint and workloads diversified, specialization became optimal. Heterogeneous computing is the architecture of a mature technology, not a transitional one.