Shared Memory
In computer systems, shared memory is a memory architecture in which multiple processors or processes access a common address space, reading and writing to the same physical or virtual memory regions. Unlike message passing, where communication is explicit and data is copied between isolated address spaces, shared memory allows direct access — a process writes to an address, and another process reads from it. This directness is both the feature and the flaw: it is the fastest form of inter-process communication when it works, and the source of the most insidious bugs when it does not.
The fundamental problem of shared memory is coordination. When multiple agents access the same data concurrently, the outcome depends on the order of operations, and that order is nondeterministic. This is the race condition: two processes read the same value, both modify it, and both write back, with one update silently lost. The solution is synchronization — mutexes, semaphores, atomic operations — but synchronization is expensive. A mutex held in contention can serialize execution, eliminating the very parallelism that multiprocessing was meant to achieve. Worse, locks compose poorly: acquiring lock A then lock B is safe only if all processes acquire them in the same order. Violate this discipline, and the system deadlocks.
Cache Coherence and the Hardware Lie
On modern hardware, shared memory is not truly shared. Each CPU core maintains private caches, and the illusion of a single unified memory is maintained by a cache coherence protocol — typically MESI or one of its variants. When one core writes to a cache line, the hardware invalidates that line in all other caches, forcing them to fetch the updated data from main memory or another cache. This protocol is invisible to the programmer but profoundly affects performance. A variable that is frequently written by multiple cores will bounce between caches, causing false sharing — a phenomenon where two unrelated variables, placed by chance in the same cache line, create spurious coherence traffic and degrade performance by orders of magnitude.
The hardware thus presents a lie: it tells software that memory is flat and uniform, when in reality it is hierarchical, distributed, and governed by protocols that introduce latency, contention, and ordering constraints. The gap between the programming model and the physical reality is the source of much complexity in systems programming. Programmers write code assuming sequential consistency — that memory operations occur in program order and are immediately visible to all processors — but modern CPUs implement relaxed memory consistency models that reorder instructions for performance. The result is that a program can be correct by intuition and wrong by execution, with failures that are intermittent and nearly impossible to reproduce.
Shared Memory and System Architecture
Shared memory architectures dominate general-purpose computing because they are compatible with the von Neumann programming model. Languages like C, C++, and Java assume a single address space, and porting them to message-passing architectures requires fundamental redesign. This compatibility is not a technical merit but a historical accident: decades of software have been written for shared memory, and the cost of rewriting it is prohibitive. The persistence of shared memory is therefore better understood as a path dependence than as an optimal choice.
In distributed systems, shared memory is approximated through distributed shared memory (DSM) systems, which use software to present a unified address space across physically separate machines. These systems are fragile and rarely used in production, because the latency of network communication makes the cache coherence problem intractable at scale. The failure of DSM is instructive: it demonstrates that the shared memory abstraction breaks down when the underlying physical layer cannot support the required coherence semantics. What works in a single server fails across a datacenter, not because of implementation flaws but because the abstraction itself assumes a locality that does not exist.
The Non-Uniform Memory Access (NUMA) architecture is an admission that shared memory does not scale. In NUMA systems, memory is physically distributed, and access time depends on which processor is accessing which memory bank. The system remains logically shared — any processor can access any memory — but the performance model is that of a distributed system. Programmers must become aware of topology, affinity, and locality, eroding the very abstraction that shared memory promised to provide. NUMA is shared memory in name only; in practice, it is a message-passing system with a deceptive interface.
The claim that shared memory is "natural" because it mirrors the way humans think about variables is a fallacy that confuses familiarity with correctness. Humans are terrible at reasoning about concurrent access to shared state, and decades of deadlock, race condition, and priority inversion bugs demonstrate this clearly. The actor model, message passing, and purely functional approaches exist precisely because shared memory has proven so difficult to use correctly. That these alternatives remain niche is not a verdict on their technical inferiority but on the inertia of existing code and the cognitive cost of paradigm shifts.