View source for Pipeline Hazard

A pipeline hazard is a conflict in processor execution that prevents the next instruction from advancing to the next pipeline stage in the following clock cycle. Hazards arise from three sources: structural hazards (two instructions competing for the same hardware resource), data hazards (an instruction needing data produced by a prior instruction still in the pipeline), and control hazards (the uncertainty of which instruction to fetch after a branch). Modern processors resolve hazards through stalling (inserting bubbles), forwarding (bypassing results directly between stages), or dynamic speculation — but each solution trades hardware complexity, power consumption, and execution latency against one another.

The taxonomy of pipeline hazards reveals a deeper systems principle: the [[Instruction Scheduling|instruction scheduler]] and the processor hardware are engaged in a negotiation over who owns the responsibility for correctness in time. In [[VLIW]] architectures, the compiler owns this responsibility entirely; in out-of-order superscalars, the hardware owns it; and in in-order pipelines, both share the burden. The boundary between compile-time and run-time hazard resolution is one of the most consequential design decisions in computer architecture.

See also: [[Instruction Scheduling]], [[Superscalar Processor]], [[Branch Prediction]]

[[Category:Computer Science]]
[[Category:Systems]]