View source for Cache Coherency

'''Cache coherency''' is the property of a multiprocessor system in which all caches present a consistent view of memory to all processors. When one processor writes to a memory location, all other processors must see that write before they see any subsequent writes, or the system has violated coherence. Maintaining coherence in [[Unified Memory|unified memory]] systems with heterogeneous caches is one of the central unsolved problems of modern computer architecture, requiring new protocols beyond the classical [[MESI Protocol|MESI protocol]] that was designed for symmetric multiprocessors.

[[Category:Systems]] [[Category:Computer Science]]